HiPC Academic Birds of a Feather (BoF)

HiPC 2014 is introducing a new session format, referred to as Academic BoFs. It is intended foster greater participation by the academic community, both domestic and international. Academic BoFs complements the main conference technical program that has peer-reviewed papers. It is expected that successful academic BoFs will advance to a full workshop format in subsequent years.

Academic BoFs focus on emerging areas of interest, where discussion among HiPC participants will help stimulate new research ideas, address specific problems, and build a research community. The BoF session format is flexible and left to the decision of the organizers, though sessions that actively engage with the participants are encouraged.

As of this posting, five Academic BoF sessions are planned for , Day 1 of the conference. All HiPC 2014 registered attendees are invited and encouraged to attend any and all of the BoF sessions. The information below is to help attendees determine areas of interest and to plan their participation.

08:30-10:30 Future Network-on-Chips
11:00-13:00 Challenges and Advances in Big Data
14:00-16:00 PhD & MS Student Research Forum
16:30-18:30 Simulation Technology – From Multicores to Data Centers
16:30-18:30 Women in Computing

Above times are tentative. Check the Advance Program for final schedule and any changes in the program. Watch for more details to be posted in coming weeks.

Technical material presented at the BoF will not appear in the proceedings of the conference. However, organizers will be encouraged to produce a one-page report on the outcome of the BoF to post on the HiPC website.

Indian Academia Liaisons

  • Kishore Kothapalli, IIIT Hyderabad, India
  • Yogesh Simmhan, Indian Institute of Science, Bangalore

Contact by email: acadbof@hipc.org

Summary of HiPC 2014 Academic BoF Sessions

Future Network-on-Chips

Organizers:
  • Basavaraj Talawar, National Institute of Technology Karnataka, Surathkal, basavaraj@nitk.edu.in
  • Bharadwaj Amrutur, Indian Institute of Science, Bangalore, amrutur@ece.iisc.ernet.in
Abstract:

Network-on-Chip (NoC) architectures are fast replacing global interconnects to alleviate the complex communication problems that arise as the number of on-chip components increase. With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate power and performance efficient communication becomes increasingly important. Network-on-Chip solutions aim to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. Further, electrical inter-connection networks are not likely to scale well to a large number of processors for energy efficiency reasons. Alternative means of on-chip communication such as wireless and photonic interconnects have emerged.

In this BoF session, we aim to bring forth and share the exciting possibilities that the future of NoC research holds. Topics of discussion are not limited to:

  • Power aware routers and routing algorithms.
  • Network interface issues in Network-on-Chips.
  • Future NoCs: Wireless, and Photonic.
  • Engineering 3D Network-on-Chips.
  • The feasibility of interconnection networks using the DNA computing paradigm.


Challenges and Advances in Big Data

Organizers:
  • Dinkar Sitaram, PESIT, dinkar.sitaram@gmail.com
  • Saumyadipta Pyne, CR Rao AIMSCS, spyne@broadinstitute.org
Abstract:

This BoF has three objectives of (i) timely dissemination of original research in the area of Big Data (ii) obtaining early feedback on research, and (iii) fostering collaboration on research in Big Data. In order to encourage cross-pollination across sub-domains, the BoF will have a broad focus and include research in all areas related to Big Data, including infrastructure, applications and algorithms. It will include presentations and a panel discussion.


PhD & MS Student Research Forum

Organizers:
  • Suresh Purini, Assistant Professor, IIIT, Hyderabad, suresh.purini@iiit.ac.in
  • Krishna Nandivada, Assistant Professor, IIT, Chennai, nvk@cse.iitm.ac.in
Abstract:

The purpose of this BoF is to provide a common platform for the Indian systems research student community where they can share their success stories, experiences and challenges in doing top quality work. This will encourage graduate students by letting them present their preliminary research and get feedback from experts.

It will include paper writing skills, discussion in understanding challenges faced in producing high impact work, and opportunities for connecting with the international research community.


Simulation Technology – From Multicores to Data Centers

Organizers:
  • Sarangi Smruti R., IIT Delhi, srsarangi@cse.iitd.ac.in
  • Banerjee Subhasis, Nokia-Siemens Research Center, subhasis@iiitd.ac.in
Abstract:

A computer architecture simulator is a vitally important tool in the design, research, and teaching of computing systems. Simulators have been used for at least the last twenty years for evaluating the efficacy of candidate designs, creating and evaluating research prototypes, and for estimating the benefits of new technology. In this session, we would like to discuss current simulation techniques, present on-going research at IIT Delhi regarding computer architecture simulation, discuss a roadmap for the Indian system's research community, and lastly formulate plans for future collaboration. In specific, the organizers would like to discuss interval based simulation, sampling, event driven simulation, Java/C# and web based simulators, and novel simulation techniques for clusters of CPUs and GPUs.

After presenting the technical details, the aim is to have a discussion with the participants regarding their awareness and requirements of simulation tools, and an overview of the available open source software support. In this context, the authors would like to present the Tejas simulator developed at IIT Delhi in collaboration with other universities. The next pass of the discussion will focus on extending the existing simulation infrastructure available in India to model large clusters, and data centers. This will most probably require a multi-institute collaboration. The details of such collaborative endeavours along with funding opportunities will be discussed, and the final goal will be to come up with a concept paper regarding the development of computer systems simulation technology in India.


Women in Computing

Organizers:
  • Arati Dixit, Defence Institute of Advanced Technology, adixit98@gmail.com
Abstract:

Goals of this session are:

  • Form a community of women in Computer Science.
  • Discuss ideas on how we can encourage more women to be active in Computer Science.
  • Build mentor relationships.
  • Discuss practices that have worked.
  • Discuss ideas on what HiPC can do to enhance the experience for women and increase their active participation. Drive implementation of those ideas for HiPC 2015.