HiPC '97 4th International Conference on High Performance Computing December 18-21, 1997 - Bangalore, India. http://www.hipc.org Co-sponsored by: IEEE Computer Society Technical Committee on Parallel Processing and ACM SIGARCH    

 

TABLE OF CONTENTS
 

ACKNOWLEDGMENTS

CONFERENCE ORGANIZATION

CONFERENCE OVERVIEW

THURSDAY, DECEMBER 18

FRIDAY, DECEMBER 19

SATURDAY, DECEMBER 20

SUNDAY, DECEMBER 21

LOCAL INFORMATION

CONFERENCE REGISTRATION FORM

HOTEL RESERVATION INFORMATION
     
 
 
 
 
 
 
 

ACKNOWLEDGMENTS
   
THE ORGANIZING COMMITTEE OF HiPC '97 GRATEFULLY ACKNOWLEDGES THE SUPPORT AND PARTICIPATION OF THE FOLLOWING ORGANIZATIONS:
Centre for Development of Advanced Computing, India
Compaq Asia Pvt. Limited
CSIR Centre for Mathematical Modelling and Computer Simulation, India
Digital Equipment (India) Limited
Indian Institute of Science, Bangalore
Indian Institutes of Technology
Infosys Technologies Limited, India
Microland Limited
Novell Software Development (India) Pvt. Limited
Silicon Graphics Systems (India) Pvt. Limited
Software Technology Parks of India
Sun Microsystems Intercontinental Operations
Supercomputer Education and Research Centre, India
Tata Information Systems Limited, India
Tata Institute of Fundamental Research (TIFR), India
Ultra Business Machines Pvt. Limited
WIPRO Limited  

   Acknowledgments | Organization | Overview | Thursday | Friday | Saturday | Sunday Tutorials | Local Info | Registration Form | Reservation Form | Table of Contents | HiPC '97 Home  

ORGANIZATION
 

GENERAL CO-CHAIRS
Viktor K. Prasanna
University of Southern California

N. Balakrishnan
Indian Institute of Science

VICE GENERAL CHAIR
D.N. Jayasimha
Intel Corporation

ADVISORY CHAIR
Vijay P. Bhatkar
Centre for Development of Advanced Computing, Pune, India

PROGRAM CHAIR
Sartaj Sahni
University of Florida

PROGRAM VICE CHAIRS
Mary Jane Irwin
Pennsylvania State University

Kai Hwang
University of Hong Kong

Jose D.P. Rolim
University of Geneva

Bhabani Sinha
Indian Statistical Institute

Albert Zomaya
The University of Western Australia

INVITED SPEAKER/PANEL COORDINATOR
Arvind
MIT

POSTER/PRESENTATION CHAIR
Prith Banerjee
Northwestern Univeristy

EXHIBITS CHAIR
S.K. Nandy
Indian Institute of Science

FELLOWSHIPS CHAIR
C. P. Ravikumar
Indian Institute of Technology, Delhi

PUBLICITY CHAIR
Kalluri Eswar
Informix Software, Inc.

FINANCE CO-CHAIRS
A. K. P. Nambiar
Centre for Development of Advanced Computing, Bangalore

Ajay Gupta
Western Michigan University

STEERING COMMITTEE

Arvind, MIT
Vijay Bhatkar, C-DAC
Wen-Tsuen Chen, National Tsing Hua University, Taiwan
Yoo Kun Cho, Seoul National University, Korea
Michel Cosnard, Ecole Normale Superieure de Lyon, France
Jose Duato, Universidad Politecnica de Valencia, Spain
Ian Foster, Argonne National Labs.
Anoop Gupta, Stanford University
Louis Hertzberger, University of Amsterdam, The Netherlands
Chris Jesshope, Massey University, New Zealand
David Kahaner, Asian Technology Information Program, Japan
Guojie Li, National Research Centre for Intelligent Computing Systems, China
Miroslaw Malek, Humboldt University of Berlin, Germany
Lionel Ni, Michigan State University
S.S. Oberoi, Dept. of Electronics, Government of India
Lalit M. Patnaik, Indian Institute of Science
Viktor K. Prasanna, USC, Chair
Jose Rolim, University of Geneva, Switzerland
Sartaj Sahni, University of Florida
Assaf Schuster, Technion, Israel Institute of Technology, Israel
Vaidy Sunderam, Emory University
Satish Tripathi, University of Maryland
David Walker, Oak Ridge National Labs.
K.S. Yajnik, Yajnik and Associates
Albert Y. Zomaya, University of Western Australia
 

NATIONAL ADVISORY COMMITTEE

R.K. Bagga
Computer and Information Centre D R D L, Hyderabad

N. Balakrishnan
Supercomputer Education and Research Centre, Indian Institute of Science

Ashok Desai
Silicon Graphics Systems (India) Private Ltd.

H. K. Kaura
Bhabha Atomic Research Centre

Hans H. Krafka
Siemens Communication Software Ltd

Ashish Mahadwar
Microland Ltd.

Pradeep Marwaha
Cray Research International Inc.

Susanta Misra
Motorola India Electronics Ltd

Sridhar Mitta
WIPRO Limited

Som Mittal
Digital Equipment (India) Ltd.

B. V. Naidu
Software Technology Park, Bangalore

N. R. Narayana Murthy
Infosys Technologies Ltd.

S. V. Raghavan
Indian Institute of Technology, Madras

V. Rajaraman
Jawaharlal Nehru Centre for Advanced Scientific Research

S. Ramadorai
Tata Consultancy Services, Bombay

S. Ramani
National Centre for Software Technology, Bombay

Uday Shukla
Tata Information Systems Ltd., Bangalore

U. N. Sinha
National Aerospace Laboratories, Bangalore

M. Vidyasagar
Centre for Artificial Intelligence and Robotics, Bangalore

G. Vijayaraghavan
Technopark, Trivandrum

PROGRAM COMMITTEE

Mikhail J. Atallah, Purdue University
Cevdet Aykanat, Bilkent University, Turkey
Raminder S. Bajwa, Semiconductor Research Laboratory, Hitachi America Ltd.
Silvano P.V. Barros, University of London, United Kingdom
Bhargab B. Bhattacharya, Indian Statistical Institute, Calcutta, India
Moreshwar R. Bhujade, Indian Institute of Technology, Powai, Mumbai, India
Chita R. Das, Pennsylvania State University
Sajal Das, University of North Texas
Eliezer Dekel, IBM Haifa Research Lab, Israel Matam Advanced Technology Centre, Israel
Hossam ElGindy, University of Newcastle, Australia
Fikret Ercal, University of Missouri, Rolla
Afonso Ferreira, Technical University of Nova Scotia, Canada
Pierre Fraigniaud, Laboratoire de l'Informatique du Parallelisme, France
Sharad Gavali, NASA
Kanad Ghose, State University of New York, Binghamton
R.K. Ghosh, Indian Institute of Technology, Kanpur, India
Mounir Hamdi, Hong Kong University of Science and Technology, Hong Kong
Oscar Ibarra, University of California, Santa Barbara
S. Sitharama Iyengar, Louisiana State University
Chris Jesshope, Massey University, New Zealand
Anand Kumar, CSIR Centre for Mathematical Modelling and Computer Simulation, India
C.P. Ravikumar, Indian Institute of Technology, New Delhi, India
J. Mohan Kumar, Curtin University of Technology, Australia
Alberto Marchetti-Spaccamela, University of Rome, Italy
Graham M. Megson, University of Reading, United Kingdom
Krishnendu Mukhopadhyaya, Jadavpur University, India
Stephan Olariu, Old Dominion University
A. Yavuz Oruc, University of Maryland at College Park
David Padua, University of Illinois at Urbana-Champaign
C. Pandu Rangan, Indian Institute of Technology, Madras, India
Murray Pearson, University of Waikato, New Zealand
Sanguthevar Rajasekaran, University of Florida
N. Ranganathan, University of South Florida
Sanjay Ranka, University of Florida
Arnold L. Rosenberg, University of Massachusetts
Catherine Roucairol, University of Versailles, France
Assaf Schuster, Technion, Israel Institute of Technology, Israel
R.K. Shyamasundar, Tata Institute of Fundamental Research, Bombay, India
Ramesh Sitaraman, University of Massachusetts
Gurindar Sohi, University of Wisconsin
Pat Teller, University of Texas at El Paso
Rajeev Thakur, Argonne National Laboratory
Marian Vajtersic, University of Salzburg, Austria Slovak Academy of Sciences, Slovakia
Mateo Valero, Universidad Politecnica de Catalunya, Spain
Toshitsugu Yuba, University of Electro-Communications, Japan
Chung-Kwong Yuen, National University of Singapore, Singapore
Emilio L. Zapata, University of Malaga, Spain
 
   Acknowledgments | Organization | Overview | Thursday | Friday | Saturday | Sunday Tutorials | Local Info | Registration Form | Reservation Form| Table of Contents | HiPC '97 Home  
 
 

Overview
 

Keynote Speakers

Dileep Bhandarkar
Director, System Architecture, Workstation Products Division, Intel Corporation "Microprocessor System Performance: Beyond the MHz and SPECint Hype"

Mick Dungworth
Vice President, SGI-CRAY
"Trends in High Performance Computing"

Chung-Jen Tan
Senior Manager, IBM T.J. Watson Research Center
"The IBM Deep Blue Chess Computer" (Deep Blue's Home)

George J Milne
Advanced Computing Research Centre, University of South Australia
"Reconfigurable Computing as a Supercomputer Replacement"

Kenichi Miura
High performance Computing Group, Fujitsu Limited
"Vector-Parallel Processing Approach to High Performance Computing"

Shuichi Sakai
Institute of Information Sciences and Electronics, University of Tsukuba, Japan
"Seamless Computing: Integrating Parallel Computing and Network Computing with Future PCs"

Panel

"Network Computing: Evolution or Revolution?"

Moderator:
Arvind, MIT

Panelists:

Anant Agarwal, MIT
Dileep Bhandarkar, Intel Corporation
Ambuj Goyal, IBM Corporation
George Milne, University of South Australia
N. Radhakrishnan, US Army
S. V. Raghavan, Indian Institute of Technology, Madras
Shuichi Sakai, University of Tsukuba

Contributed Papers

There will be 77 contributed papers from 18 countries. These will be presented in 12 sessions. In addition, there will be a special session and a mini-panel on Instruction Level Parallelism.

Poster/Presentation Session

In addition to parallel sessions of contributed papers, a plenary poster/presentation session emphasizing novel applications of high performance computing will be held on Friday. It will offer a brief presentation time for each poster and will be followed by a walk-up and talk setting.

For details contact the Poster/Presentation Chair.

Prith Banerjee
Northwestern University
(banerjee@eecs.nwu.edu)

Tutorials

Programming Parallel Computers for High Performance
J. Ramanujam
Louisiana State University
P. Sadayappan
Ohio State University

Emerging Internet Technologies and Protocols
Guru Parulkar
Washington University, St. Louis

Mobile and Wireless Computing
Prathima Agrawal
AT&T Labs

Performance Modeling of High-Performance Systems
A.J.C. van Gemund
Delft University of Technology
S.K. Nandy
Indian Institute of Science

Internet, Java, and Java Computing in Practice
Rajkumar
Centre for Development of Advanced Computing, Bangalore

High Performance Networked Multimedia Systems
Guru Parulkar
Washington University, St. Louis

Understanding ATM Networks
Saragur Srinidhi
FORE Systems
 

Exhibits/Vendor Presentations

Companies and R & D laboratories are encouraged to display their exhibits at the meeting as well as present their products in the Industrial Track sessions.

For details, contact the Exhibits Chair:

S.K. Nandy
Supercomputer Education and Research Centre
Indian Institute of Science Bangalore 560012, India
Fax: +91 (80) 334 6648
Vox: +91 (80) 334 1811
(nandy@serc.iisc.ernet.in)

Additional details will be available on the Web at www.hipc.org/hipc97
 
 
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Thursday, Dec.18
 

8:25 AM - 8:30 AM
Opening Remarks

Viktor Prasanna
N. Balakrishnan
Sartaj Sahni

8:30 AM - 9:30 AM
Keynote Address

"Seamless Computing: Integrating Parallel Computing and Network Computing with Future PCs"

Sun-UBM Distinguished Speaker
Shuichi Sakai
Institute of Information Sciences and Electronics,
University of Tsukuba, Japan 

10:00 AM - 11:30 AM
Session I-A
DBMS and ILP
Chair: Mateo Valero Universidad Politecnica de Catalunya, Spain

Concurrency Control of Nested Cooperative Transactions in Active DBMS
Prithwish Kangsabanik, Rajib Mall, and Arun Kumar Majumdar, Indian Institute of Technology, Kharagpur

Parallel DataCube Construction for High Performance On-Line Analytical Processing
Sanjay Goil and Alok Choudhary, Northwestern University

A Comparison of Two Context Allocation Approaches for Fast Protected Calls
Pavel Vasek and Kanad Ghose, State University of New York, Binghamton

A Different Approach to High Performance Computing
Henk Corporaal, Delft University of Technology

A Study of Tree-Based Control Flow Prediction Schemes
Bunith Cyril and Manoj Franklin, Clemson University

Classification and Performance Evaluation of Simultaneous Multithreaded Architectures
B. Hari Krishna and R. Govindarajan, Indian Institute of Science 

10:00 AM - 11:30 AM
Session I-B
Applications
Chair: Anand Kumar CSIR Centre for Mathematical Modeling and Computer Simulation, India

Mapping of Neural Network Models onto Massively Parallel Hierarchical Computer Systems
Sudipta Mahapatra, Regional Engineering College, Rourkela

Interconnection Network Behavior on a Multicomputer in the Parallelization of the MPEG Coding Algorithm: Worm-Hole vs Packet-Switching Routing
Teresa Olivares, Pedro Cuenca, Francisco J. Quiles, Antonio Garrido, Jose L. Sanchez, Universidad de Castilla, La Mancha, and J. Duato, Universidad Politecnica de Valencia

Parallel Interactive Virtual Machining on Shared Memory Multiprocessors
N. Mahesh and S. Manohar, Indian Institute of Science

A Memory-Optimized Visualization System for Limited-Bandwidth Multiprocessing Environments
Asish Law, Nichimen Graphics, Inc. and Roni Yagel, Ohio State University

On Improving the Performance of Sparse Matrix-Vector Multiplication
James B. White, III, Ohio Supercomputer Center and P. Sadayappan, Ohio State University

Parallelization of Finite Volume Computations for Heat Transfer Application Using Unstructured Mesh Partitioning Algorithms
Chaman Singh Verma and V. C. Venkata Rao, Pune University

Parallel Spectral-Element Simulations in Earth and Space Sciences
Anil Deane, Susan Sakimoto, NASA Goddard Space Flight Center, Einar Ronquist, and Edward Bullister, Nektonics, Inc.  

Dec. 18 12:00 NOON - 1:30 PM
Session II-A Data Migration and Caching
Chair: Murray Pearson University of Waikato, New Zealand

A New Consistency Protocol Implemented in the CAliF System
H. Guyennet, J-C. Lapayre, and M. Trehel, UFR Sciences et Techniques

A Floating-Point Validation Suite for High-Performance Shared and Distributed Memory Computing Systems
S. K. Ghoshal, Indian Institute of Science

Effectiveness of Caching Policies for a Web Server
A. L. Narasimha Reddy, Texas A&M University

A New Voting Based Hardware Data Prefetch Scheme
Gurmeet Singh Manku, Mukul R. Prasad, and David A. Patterson, University of California, Berkeley

Lazy Home Migration for Distributed Shared Memory Systems
Sandra Baylor, Kattamuri Ekanadham, Joefon Jann, Beng-Hong Lim, and Pratap Pattnaik, IBM T.J. Watson Research Center

A Cost Model for Distributed Shared Memory Using Competitive Update
Jai-Hoon Kim and Nitin H. Vaidya, Texas A&M University 

12:00 NOON - 1:30 PM
Session II-B Algorithms
Chair: Assaf Schuster Technion, Israel

Parallel Algorithms for the Longest Common Subsequence Problem
K. Nandan Babu, Wipro Systems, and Sanjeev Saxena, Indian Institute Of Technology, Kanpur

Applications of BSR Model of Computation for Subsegment Problems
Laurent Bergogne and Christophe Cerin, Universite de Picardie Jules Verne

An Optimal Parallel Algorithm for the All-Nearest-Foreign-Neighbors Problem in Arbitrary Dimensions
T. Graf, Research Centre Julich, N. S. Janaki Latha, Indian Institute of Technology, Madras, V. Kamakoti, Indian Institute of Science, and C. Pandu Rangan, Indian Institute of Technology, Madras

A High Performance Two Dimensional Scalable Parallel Algorithm for Solving Sparse
Triangular Systems
Mahesh V. Joshi, George Karypis, and Vipin Kumar, University of Minnesota

Parallel Algorithms for Vehicle Routing Problems
Arvind Gupta and Ramesh Krishnamurti, Simon Fraser University

Adaptive Multivariate Integration using MPI
Elise de Doncker, Ajay Gupta, and Min Guo, Western Michigan University

Integer Sorting Algorithms for Coarse-Grained Parallel Machines
Khaled Alsabti, Syracuse University and Sanjay Ranka, University of Florida
 

Thursday, Dec. 18
3:00 PM - 4:00 PM
Keynote Address

"Trends in High Performance Computing"
Mick Dungworth
Vice President, SGI-CRAY 

4:30 PM - 6:00 PM
Session III-A Programming and Languages
Chair: Y. N. Srikant Indian Institute of Science

Supporting Unbounded Process Parallelism in the SPC Programming Model
Arjan J. C. van Gemund, Delft University of Technology

Design of a Parallel C Language for Distributed Systems
Kyoungseok Lee, Jinmee Kim, and Youngchoon Woo, ETRI

ELMO: Extending (Sequential) Languages with Migratable Objects - Compiler Support
R. J. Richards, B. Ramkumar, and S. G. Rathnam, University of Iowa

Parallel Real-Time Systems: Formal Specification
Alok Choudhary, Northwestern University, Vijay Gehlot, University of Pennsylvania, and B. Narahari, George Washington University

An Object Oriented System for Developing Distributed Applications
Gurdip Singh and Yiwen Gu, Kansas State University

Parallel Program Design in Visual Environment
Elena Trichina, University of South Australia and Juha Oinonen, CSC-FUNET
  

4:30 PM - 6:00 PM
Session III-B Load Balancing and Scheduling
Chair: Henk Corporaal Delft University of Technology

Dynamic Scheduling of Parallelizable Tasks and Resource Reclaiming in Real-Time Multiprocessor Systems
G. Manimaran and C. Siva Ram Murthy, Indian Institute of Technology, Madras

Load Balancing Sequences of Unstructured Adaptive Grids
Rupak Biswas and Leonid Oliker, NASA Ames Research Center

A Hierarchical Processor Scheduling Policy for Distributed-Memory Multicomputer Systems
Sivarama Dandamudi and T. K. Thyagaraj, Carleton University

Sparse Matrix Decomposition with Optimal Load Balancing
Ali Pinar and Cevdet Aykanat, Bilkent University

Parallel Domain Decomposition and Load Balancing Using Space-Filling Curves
Srinivas Aluru, New Mexico State University and Fatih E. Sevilgen, Syracuse University

Characterizing Vulnerability of Parallelism to Resource Constraints
V. Vivekanand, K. Gopinath, Indian Institute of Science, and Pradeep Dubey, IBM Watson Research Center

Load Balancing Using Symmetric Broadcast Networks: A PVM-Based Comparative Performance Study
Sushil K. Prasad, Georgia State University and Sajal K. Das, University of North Texas
 
 
   Acknowledgments | Organization | Overview | Thursday | Friday | Saturday | Sunday Tutorials | Local Info | Registration Form | Reservation Form| Table of Contents | HiPC '97 Home  
 

Friday, Dec. 19



8:30 AM - 9:30 AM

Keynote Address

"Vector-Parallel Processing Approach to High Performance Computing"
Kenichi Miura High performance Computing Group, Fujitsu Limited.

10:00 AM - 11:30 AM
Industrial Track Session I TBA

12:00 NOON - 1:30 PM
Industrial Track Session II TBA

3:00 PM - 4:00 PM
Keynote Address

Chung-Jen Tan
Senior Manager, IBM T.J. Watson Research Center
"The IBM Deep Blue Chess Computer" (Deep Blue's Home)

4:30 PM - 6:00 PM
Panel

"Network Computing: Evolution or Revolution?"

Moderator: Arvind, MIT

Panelists:
Anant Agarwal, MIT
Dileep Bhandarkar, Intel Corporation
Ambuj Goyal, IBM Corporation
George Milne, University of South Australia
N. Radhakrishnan, US Army
S. V. Raghavan, Indian Institute of Technology, Madras
Shuichi Sakai, University of Tsukuba

6:30 PM - 8:00 PM
Reception and Poster Session

Poster Session
Chair: Prith Banerjee Northwestern University

Studies in Asynchronous Recovery
Abhijit R. Bhaware and Pushpak Bhattacharya, Indian Institute of Technology, Bombay

Towards Lower Processor Bounds for All Pairs Shortest Paths
Malay Haldar and Debojyoti Dutta, Indian Institute of Technology, Kharagpur

Xcent-Net Interconnection Network for a High Performance Parallel Computing Server
Jong-Seok Hahn, Kyoung Park, Won-Sae Sim, Woo-Jong Hahn, Suk-Han Yoon and Seong-Woon Kim, ETRI, Korea

An SMP Node for High-Speed Parallel Computer SPAX
Seong-Woon Kim, Sang-Seok Shin, Chul-Ho Won and Sang-Man Moh, ETRI, Korea

Exploiting Multithreading Through Control and Data Dependence Speculation
Pedro Marcuello and Antonio Gonzalez, Universitat Politecnica de Catalunya, Spain

Multi-window FTP Systems in Java: A Network Client
Rajkumar and Bijo Thomas, CDAC, Bangalore

Call Admission Control and Routing in ATM Networks for Multimedia Communications
Dilip R. Pandir and C.P. Ravikumar, Indian Institute of Technology, New Delhi

A Modular Approach for Developing Enhanced Orthogonal Multiprocessor Systems
Leonel Sousa, INESC, Portugal

Principle and Algorithms of Real-Time Parallel Processing For Distributed Processor
Wassily A. Khlebnikov, Softloys Corporation, Russia

8:00 PM - 10:00 PM
Conference Banquet
 
   Acknowledgments | Organization | Overview | Thursday | Friday | Saturday | Sunday Tutorials | Local Info | Registration Form | Reservation Form| Table of Contents | HiPC '97 Home  
 

Saturday, Dec. 20


8:30 AM - 9:30 AM
Keynote Address

"Reconfigurable Computing as a Supercomputer Replacement"
Infosys Distinguished Speaker
George J Milne
Advanced Computing Research Centre, University of South Australia 

10:00 AM - 11:30 AM
Session IV-A Architecture
Chair: Mary Jane Irwin Pennsylvania State University

Gradient Method Based Design Methodology for Time and Area Optimization of a Pipelined Attached Processor Architecture
K. Rajesh Jagannath and Glenn A. Gibson, University of Texas, El Paso

PiSMA: An Upgradeable Fault Tolerant Approach to Parallel Processing
Dimitris Lioupis, Andreas Pipis, and Michael Stefanidakis, University of Patras

Single Step Undirected Reconfigurable Networks
Yosi Ben-Asher, Haifa University and Assaf Schuster, Technion

Applying Time Warp to CPU Design
Murray Pearson, Richard Littin, David McWha, and John Cleary, University of Waikato

Compact and Flexible Linear-Array-Based Implementations of a Pipeline of Multiprocessor Modules for High Throughput Applications
Soo-Young Lee and Gautam D. Ghare, Auburn University

Fast Parallel Multiplier Schemes Using Incomplete Large Parallel Counters and Large Shift Switches
Rong Lin, State University of New York, Geneseo 

10:00 AM - 11:30 AM
Session IV-B Routing
Chair: C. P. Ravikumar Indian Institute of Technology, Delhi

Probabilistic Routing in Wavelength-Routed Multistage, Hypercube, and Debruijn Networks
G. Venkatesan, G. Mohan, and C. Siva Ram Murthy, Indian Institute of Technology, Madras

LIFE: a Limited Injection, Fully adaptivE, Recovery-Based Routing Algorithm
Fabrizio Petrini, Universita di Pisa, Jose Duato, Pedro Lopez, and Juan-Miguel Martinez, Universidad Politecnica de Valencia

A Flow Control Mechanism to Prevent Message Deadlock in k-ary n-cube Networks
C. Carrion, R. Beivide, J. A. Gregorio, and F. Vallejo, Universidad de Cantabria

Improving the Efficiency of Adaptive Routing in Networks with Irregular Topology
F. Silla and J. Duato, Universidad Politecnica de Valencia

On Measuring the Performance of Adaptive Wormhole Routing
Loren Schwiebert, Wayne State University and D. N. Jayasimha, Intel Corporation

Adaptive Multimodule Routers
Rajendra V. Boppana, University of Texas, San Antonio and Suresh Chalasani, University of Wisconsin-Madison 

10:00 AM - 11:30 AM
Session IV-C ILP Architectures and Compiler Issues
Chair: R. Govindarajan Indian Institute of Science

Simultaneous Multithreaded Vector Architecture: Merging ILP and DLP for High Performance
R. Espasa and M. Valero, Universidad Politecnica de Catalunya, Barcelona

Highly Accurate Data Value Prediction
Kai Wang and Manoj Franklin, Clemson University

Virtual Registers
A. Gonzalez, M. Valero, J. Gonzalez, and T. Monreal, Universidad Politecnica de Catalunya, Barcelona

Code Optimization as a Side Effect of Instruction Scheduling
Rajiv Gupta, University of Pittsburgh

Saturday, Dec. 20 

12:00 NOON - 1:30 PM
Session V-A Parallel I/O and Multithreaded Systems
Chair: Sriram Vajapeyam Indian Institute of Science

Building Reliable Distributed Programs with File Operations
Jinsong Ouyang and Piyush Maheshwari, University of New South Wales

Predicting the Speedup of Multithreaded Solaris Programs
Lars Lundberg and Mikael Roos, University of Karlskrona/Ronneby

Evaluating the Performance Implications of Binding Threads to Processors
Lars Lundberg, University of Karlskrona/Ronneby

Global I/O Optimizations for Out-of-Core Computations
Mahmut Taylan Kandemir, Northwestern University, Meenakshi Kandaswamy, Syracuse University, and Alok Choudhary, Northwestern University

Modeling Multi-Threaded Architectures in PAMELA for Real-Time High-Performance Applications
S. Balakrishnan, S. K. Nandy, Indian Institute of Science, and Arjan J. C. van Gemund, Delft University of Technology

FP-Map - An Approach to the Functional Pipelining of Embedded Programs
Ireneusz Karkowski and Henk Corporaal, Delft University of Technology 

12:00 NOON - 1:30 PM
Session V-B ICNs and Virtual Channels
Chair: Sanjay Ranka University of Florida

A Tight Layout of Cube-Connected Cycles
Guihai Chen and Francis C. M. Lau, University of Hong Kong

Mixed-Autonomy Interconnect for Reconfigurable SIMD Arrays
Raminder S. Bajwa, Hitachi America Ltd., Robert M. Owens, and Mary Jane Irwin, Pennsylvania State University

Wormhole Routing for Complete Exchange in Multi-Mesh
Mallika De, Bhaktipada Kundu, and Bhabani P. Sinha, Indian Statistical Institute

Distributed Delay Constrained Multicast Path Setup Algorithm for High Speed Networks
Ramnik Bajaj, C. P. Ravikumar, and Suresh Chandra, Indian Institute of Technology, Delhi

Virtual Control Channel and Its Application to the Massively Parallel Computer RWC-1
Takashi Yokota, Mitsubishi Electric Corporation, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, and Shuichi Sakai, University of Tsukuba

Prioritized Demand Multiplexing (PDM): A Low-Latency Virtual Channel Flow Control Framework for Prioritized Traffic
A-H. Smai, KTH, D. K. Panda, Ohio State University, and L-E. Thorelli, Royal Institute of Technology

12:00 NOON - 1:30 PM

Mini-panel

"Has Exploitable ILP Reached a Point of Diminishing Returns?"

Moderator:
R. Govindarajan, Indian Institute of Science

Panelists:
Anant Agarwal, MIT
Manoj Franklin, Clemson University
K. Gopinath, Indian Institute of Science
Vinod Kathail, HP Labs
Krishna Palem, NYU
Vivek Sarkar, IBM/MIT
Mateo Valero, Universidad Politecnica de Catalunya, Barcelona

Saturday, Dec. 20
3:00 PM - 4:00 PM
Keynote Address

"Microprocessor System Performance: Beyond the MHz and SPECint Hype"

Dileep Bhandarkar
Director, System Architecture, Workstation Products Division, Intel Corporation 

4:30 PM - 6:00 PM
Session VI-A Distributed Systems
Chair: N. Radhakrishnan US Army

An Efficient Token-Based Algorithm for Distributed Mutual Exclusion
P. K. Dash, Motorola India Electronics Ltd. and R. C. Hansdah, Indian Institute of Science

Independent Global Snapshots in Large Distributed Systems
Subhash Bhalla, University of Aizu and M. V. Sreenivas, Lucent Technologies India Private Ltd.

Low-Latency Reductions on a Network of Workstations
Sudhir Srinivasan, Margaret J. Lyell, Jeff W. Wehrwein, Mystech Associates, Inc., and Paul F. Reynolds, Jr., University of Virginia

Modelling of Generalised Distributed Systems Using Extended Colored Net
S. Mukherjee, Bengal Engineering College and S. Bhattacharya, Indian Institute of Management

Communication Cost Estimation and Global Data Partitioning for Distributed Memory Machines
S. R. Prakash and Y. N. Srikant, Indian Institute of Science

HOLMES: a Tool for Monitoring Heterogeneous Architectures
Antonio Corradi and Cesare Stefanelli, Universita di Bologna

System Resource Accounting in a Heterogeneous Distributed Computing Environment
Basanta Kumar Rana, Mathew Jacob T., and N. Balakrishnan, Indian Institute of Science 

4:30 PM - 6:00 PM

Session VI-B Image Processing
Chair: Cevdet Aykanat Bilkent University, Turkey

On Unsupervised Segmentation of Color Texture Images
R. Krishnamoorthi and P. Bhattacharyya, Indian Institute of Technology, Kharagpur

Recursive Gabor Transform for Images of Very Large Size and Design of Massively Parallel Architecture
N. Venkateswaran, M. Venkatachalam, S. Swaminathan, and C. Srinivasan, Sri Venkateswara College of Engineering

A New Orthogonal Multiprocessor and Its Application to Image Processing
Leonel Sousa and Moises Piedade, Instituto de Engenharia de Sistemas e Computadores

Custom Virtual Memory Policies for an Image Reconstruction Application
Vasudha Govindan, Yoonho Park, Olin Johnson, and Z. Hong Zhou, University of Houston

A Computer Aided Architecture Design Tool Aimed at Image Processing Applications
Pascal Collet, Aerospatiale Missiles, Gerard Ramstein, IRESTE - Laboratoire SEI, and Bernard Longuet, Aerospatiale Missiles

A Document Image Analysis System on Parallel Processors
Shamik Sural, CMC limited and P. K. Das, Jadavpur University

Efficient Algorithms for Feature Extraction from Oceanographic Images
Kiran K. Simhadri and S. S. Iyengar, Louisiana State University
 
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Sunday, Dec. 21
   
 

8:30 AM - NOON
TUTORIAL 1
Programming Parallel Computers for High Performance
J. Ramanujam Louisiana State University
P. Sadayappan Ohio State University

Audience: This tutorial is targeted primarily at graduate students, application developers, and computer/computational scientists interested in parallel computing. Knowledge of FORTRAN/C programming will be assumed; no prior parallel programming experience will be assumed. The intended level of presentation is 75% beginner and 25% intermediate. Course Description: The performance of programs on modern computers depends on a variety of factors such as the memory access pattern, available fine-grained operation-level parallelism, and data/computation distribution among processors. This tutorial will cover issues that are central to performance optimization of parallel programs, addressing factors that influence single-node performance and multi-node speedup. Examples from application domains such as Computational Fluid Dynamics and Computational Electromagnetics, with performance data from current parallel systems (including distributed memory machines like the IBM SP-2 and Cray T3E, as well as scalable shared memory machines like the Convex Exemplar and SGI Origin) will be used to illustrate the impact of algorithm design/implementation choices on achieved performance.

Lecturers:
J. Ramanujam received his Ph.D. from the Ohio State University in 1990 and is an Associate Professor in the Department of Electrical and Computer Engineering at Louisiana State University. He received an NSF Young Investigator Award in 1994.

P. Sadayappan received his Ph.D. from the State University of New York at Stony Brook in 1983 and is a Professor in the Department of Computer and Information Science at the Ohio State University.

8:30 AM - NOON
TUTORIAL 2
Emerging Internet Technologies and Protocols
Guru Parulkar Washington University, St. Louis

Audience: Anybody who is interested in or responsible for planning and managing Intranets and Internets and researchers and educators interested in computing and communications. Course Description: Internet has seen an explosive growth for the past decade and there is a strong evidence that it has or will soon become a very important infrastructure for education, research, business, commerce, entertainment, and other aspects of our regular life. As the Internet continues to grow, provides higher and higher data rates, and support a variety of applications including multimedia, the underlying core set of technologies and protocols are also undergoing significant changes. The purpose of this tutorial is to review the emerging Internet technologies and protocols, their potential impact, and to identify unresolved issues (i.e., research opportunities). Specifically, the tutorial will cover the following topics: review of existing Internet protocols (UDP/TCP/IP) and technologies (IP routers and protocol implementations), integrated services over Internet, RSVP, IPv6, RTP, gigabit IP routers and switches, and multimedia applications.

Lecturer:
Guru M. Parulkar is a Professor of Computer Science at Washington University in St. Louis and Director of the Applied Research Laboratory. He received his Ph.D. in Computer Science from the University of Delaware (1987). His research emphasis has been on the design, implementation, and evaluation of high performance Internetworking and multimedia systems. His research has been supported by a number of federal and industrial organizations. He is the Publications Editor and a Technical Editor of the ACM/IEEE Transactions on Networking, is an editor of The IEEE Network, served as a guest editor for its special issue on Local Area ATM Networks, and served as a co-guest editor for the IEEE JSAC special issue on Gigabit Network Protocols. He has been the Program Committee Chair of NOSSDAV'97 and IEEE HPCS'97. He has also served on several NSF review panels and site visit teams, and a number of IEEE and ACM conference program committees.

8:30 AM - NOON
TUTORIAL 3
Mobile and Wireless Computing
Prathima Agrawal AT&T Labs

Audience: Researchers as well as practicing engineers interested in recent developments and design issues in the above topic. The tutorial is suited to both computing and communication professionals. In addition, service providers (PCS, cellular, Internet, for example), as well as computing and communication equipment developers will find value in the tutorial contents. Course Description: The tutorial is on the architecture and networking technology, and design techniques, underlying mobile multimedia computing systems. We shall first present the current state of the art and introduce various core concepts including wireless access, mobility management, and location management in existing cellular voice and mobile IP systems. Next, we shall focus on the emerging mobile multimedia networked computing systems. We shall describe research issues in (i) multimedia-oriented network infrastructure capable of supporting mobility and wireless access, and (ii) portable wireless terminals for mobile multimedia access. The tutorial shall present approaches to problems such as providing end-to-end quality of service (latency, synchronization) for mobile multimedia applications. The tutorial will end with a presentation of application level issues such as adaptation to mobility events, and the performance and energy efficiency impact of the terminal-network computation partitioning. Throughout the tutorial, we shall use the SWAN (Seamless Wireless ATM Network) system from Bell Labs and other research systems elsewhere as examples.

Lecturer:
Prathima Agrawal heads the Networked Computing Technology Department at AT&T Labs. Earlier, she was head of the the Networked Computing Research Department at Lucent Bell Laboratories in Murray Hill, NJ. She received her BE and ME degrees in Electrical Communication Engineering from the Indian Institute of Science, Bangalore, India and a Ph.D. degree in Electrical and Computer Engineering from the University of Southern California. Her research interests are computer networks, mobile computing, multimedia, parallel processing architectures, and VLSI CAD. She has over 130 technical publications and holds 8 US patents. She is a Fellow of the IEEE.

8:30 AM - NOON
TUTORIAL 4
Performance Modeling of High-Performance Systems
A.J.C. van Gemund Delft University of Technology, The Netherlands
S.K. Nandy Indian Institute of Science, Bangalore

Audience: Researchers in high-performance computing, graduate students, application developers, hardware architects, and practicing engineers interested in performance modeling of complex applications in current day high performance computing environments. The intended level of presentation is 30% beginner, 50% intermediate, and 20% advanced. Basic familiarity with shared-memory and distributed-memory computer architecture and programming techniques is assumed. Course Description: In high performance computing, performance of applications can be extremely sensitive to programming parameters such as task and data partitioning, and machine parameters such as computation and communication delays. In the design of parallel architectures and programs, performance models can provide valuable feedback in the early design stage and assist in the diagnosis of potential sources of performance bottlenecks observed in practice. The primary goal of the tutorial is to provide an understanding of the basic techniques necessary to derive a performance model of a parallel application on a target machine. In the tutorial, we will introduce a simulation technique based on the PAMELA language that provides a simple tool to formalize application and target machine in terms of an executable performance model. The simulation model can also be used as the basis for alternative, analytic techniques such as queuing analysis and stochastic Petri net analysis, as well as approximate analytic techniques.

Lecturers:
A.J.C. van Gemund has been on the faculty of the Electrical Engineering department, Delft University of Technology since 1992. Prior to this, he worked many years in Dutch industry as well as for the Dutch National Organization for Applied Scientific Research. His research interests are in the area of performance modeling, programming models, and compilation techniques, all with an emphasis on parallel and distributed systems.

S. K. Nandy is on the faculty of Supercomputer Education and Research Centre of the Indian Institute of Science, Bangalore since 1982. His interests include domain specific high performance architectures, multi-threaded and dataflow computing, architecture synthesis of VLSI systems, hardware-software co-design, and parallel algorithms.

Sunday, Dec. 21
1:30 PM - 5:00 PM
TUTORIAL 5
Internet, Java, and Java Computing in Practice
Rajkumar Centre for Development of Advanced Computing, Bangalore

Audience: Application (Sequential and Parallel/Distributed) Programmers, System Designers, and Concurrent Programming Interface Developers. The intended level of presentation is 50% beginner, 30% intermediate, and 20% advanced. The tutorial assumes a knowledge of C or C++. Course Description: Today, the key areas of computing are the Internet, Intranets, and the World Wide Web (WWW). A new programming language well suited to the network environment is the object oriented language Java developed by Sun Microsystems. This tutorial will introduce the Java programming language and explain how high performance (computing), networking (communication), and imaging can be integrated into it. It will illustrate Java's WWW-related strengths through simple examples. It will also demonstrate Java's potential for use with selected non-WWW applications such as multithreaded servers. Finally, the strengths and weaknesses of Java are examined.

Lecturer: Rajkumar is a Member of the Technical Staff, Operating Systems Group, Centre for Development of Advanced Computing, Bangalore, India. He received the Bachelor of Engineering degree in Computer Science from the University of Mysore and the Master of Engineering degree in Computer Science from the University of Bangalore. He is a visiting faculty member at the Bangalore University and also conducts a popular course on Java by email which is broadcast around the globe through the Internet. He is the coauthor of "Microprocessor x86 Programming" and "Object Oriented Programming with C++". His research interests are in programming paradigms and operating environments for parallel and distributed computing.

1:30 PM - 5:00 PM
TUTORIAL 6
High Performance Networked Multimedia Systems
Guru Parulkar Washington University, St. Louis

Audience: Anybody who is interested in or responsible for planning and managing IT infrastructure and researchers and educators interested in multimedia computing and communications. Course Description: With the advent of high speed (155 Mbps to Gbps) networks and ever increasing computing power of computers, desktop networked multimedia systems and applications are becoming possible and a topic of intense research and commercial development. These trends have forced researchers to reconsider workstation and server architectures, protocol designs and their implementations, and other building blocks of computing and networking. A number of research groups have been actively working on these and other related topics with promising results. The purpose of this tutorial is to review research in these areas and to help understand implications of early results on future of distributed computing and networking. The emphasis of the tutorial will be on Multimedia application scenarios and their requirements Operating system support and protocol implementations for QoS guarantees Host-network interfacing and desk area networks Multimedia server architectures Integrated services on the Internet Custom hardware vs all software implementations Networked multimedia tools and applications Lecturer: See Lecturer information in Tutorial 2.

1:30 PM - 5:00 PM
TUTORIAL 7
Understanding ATM Networks
Saragur Srinidhi FORE Systems

Audience: MIS, CIO, and the network Management professionals responsible for the planning, implementation of LANs, WANs and internetworks. A background in networks is required. Course Description: What is ATM? How is it different from today's networking technologies? This tutorial is designed to acquaint the participants with emerging technology and to describe some of the concepts embodied within it. Current networking needs demand that new services be added dynamically to meet performance demands while securing information and application access at the same time. Guidelines based on number of users or servers are no longer adequate for selection of the core backbone. Merely adding bandwidth to existing infrastructures fails to support emerging network applications and services- this will force users to perform significant, unplanned, upgrades of their LAN infrastructures which may require "writing-off" current infrastructures within the next five years. ATM is the technology that provides high-speed switching along with the ability to support mixed traffic types. The tutorial will explain how ATM networking solutions can provide strategic advantages to organizations today.

Lecturer: Saragur M. Srinidhi received his M.S. and Ph.D. degrees in Electrical Engineering from Cleveland State University, USA in 1988 and 1992, respectively. He was a Telecommunications Consultant with BP America in Cleveland, Ohio and later with Sterling Software Federal Group based at NASA Lewis Research Center in Cleveland where he was a Senior Consulting Engineer with the High-Performance Networks Group. He was a Principal Investigator for NASA Advanced Communications Technology Satellite (ACTS) project to effect ATM networking over satellites and has extensively worked on prototyping wide-area ATM networks in support of dispersed applications. He is currently the Country Manager for FORE Systems Inc. and manages the business operations in India. His research interests are in Performance modeling, Congestion control, and Transport level issues in ATM. He is a member of the Graduate Faculty at Cleveland State University and is a member of the IEEE and ACM.
 
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Local Information


The meeting will be held at the following address.

The Taj Residency
41/3, Mahatma Gandhi Road
Bangalore 560 001, India
Tel: +91-80-558-4444
Fax: +91-80-558-4748

About Bangalore:

Bangalore is the capital of the state of Karnataka and is the fifth largest city in India. The city is home to the Indian Institute of Science, many aerospace and high technology industries including the Centre for Development of Advanced Computing and is often called the Silicon valley of India. It is about 250 Kms from Madras and is about 800 Kms from Bombay. Situated at an altitude of approximately 1000 meters above sea level, Bangalore has a population of over three million people. The city's prominent buildings include the Vidhana Soudha which is the Legislative building and the palace of the former maharaja of Mysore. Many historic and archeological sites can be easily reached from Bangalore.

Visa and Passports:

All participants who are not citizens of India must obtain a valid visa from Indian Consulates or High Commissions. The procedure may take some time, check with your travel consultant in advance. Currency: The currency is the Indian Rupee. The conversion rate at the time of this publication is 1 US $ to Rs. 35.80. Credit cards are accepted in most luxury hotels. The Reserve Bank of India may have certain restrictions on converting Rupees to other currencies. For details, check with an Indian Consulate or your travel consultant.

Time and Weather:

The Indian Standard Time(IST) is 5 1/2 hours ahead of the Greenwich Mean Time(GMT) and is 13 1/2 hours ahead of the U. S. Pacific Standard Time(PST). In December/January the weather is mildly tropical with temperatures averaging about 22 degrees Celsius (approx. 70 degrees Fahrenheit) during the day and about 14 degrees Celsius (approx. 55 degrees Fahrenheit) during the night.

Travel:

Most international carriers fly to India. Indian Airlines and several private airlines connect Bangalore with major cities on a daily basis. It is advisable to make reservations early as travel is heavy during the months of December and January. The meeting does not endorse any travel agency, however, to assist international travelers a block of seats has been reserved. You may contact Globalink Travels in the Los Angeles area at +1 818-972-9525 for details.

Accommodation:

A block of rooms has been reserved for the meeting participants at the Taj Residency. Please make room reservations directly with the hotel using the hotel reservation information provided. The Taj Residency is a 5 star hotel situated on Mahatma Gandhi road, which is the city's most famous promenade. The airport is less than 10 Kms from the hotel. The cost of the ride to or from the airport can vary, and a one-way taxi ride will cost around US $6 including tip. The deadline for reservations is November 1. Since December is a busy time for travel in India, you may want to reserve your room in advance.

 
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HiPC '97 HOTEL RESERVATION INFORMATION
 

Travel to India during the month of December is usually very heavy. Accommodations at special HiPC rates have been reserved at The Taj Residency(the venue of the meeting). The Taj Residency is a 5 star hotel.

The Taj Residency
41/3, Mahatma Gandhi Road
Bangalore 560 001, India
Tel: +91-80-558-4444
Fax: +91-80-558-4748

Standard rooms:
Single US$ 125 + Tax
Double US$ 135 + Tax

Residency rooms:
Single US$ 145 + Tax
Double US$ 155 + Tax

The Residency rooms are located on the higher floors, have their own business lounges where in breakfast is served and evening cocktail hour is held. Also, 24 hour valet service is available on these floors. Taxes applicable would be 15% Luxury tax, 0.75% MRTS cess and 10% Expenditure tax. The rates include breakfast.

Hotel Reservation Deadline: November 1, 1997.

To make reservation, contact the hotel, note you will be attending HiPC'97 and furnish the following information.

1. Name -
2. Affiliation
3. Address -
4. Phone & Fax
5. Accommodations requested (Standard/Residency) and (Single/Double)
6. Number in party (Ages of Children)
7. Arrival & Departure (Date/Time)
8. Credit Card Guarantee

Please note the following.

1. THE DEADLINE TO MAKE RESERVATIONS TO HOLD THE BOOKING ON A CONFIRMED BASIS IS NOVEMBER 1, 1997. AFTER
    NOVEMBER 1, ROOMS WILL BE CONFIRMED SUBJECT TO AVAILABILITY.

2. RESERVATIONS MUST BE GUARANTEED USING A CREDIT CARD.

3. ANY CANCELLATIONS OR AMENDMENTS HAVE TO BE MADE BEFORE 2ND DECEMBER 1997, AFTER WHICH ONE NIGHT'S ROOM
    RATE WOULD BE CHARGED AS RETENTION CHARGES.

4. ROOM WILL BE RELEASED AT 6 P.M. ON THE DAY OF THE RESERVATION.

5. THE ABOVE RATES ARE VALID FROM DECEMBER 15, 1997 TO DECEMBER 25, 1997.

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HiPC '97 ADVANCE REGISTRATION FORM
 

This form can also be down-loaded from http://www.hipc.org/hipc97
 

PLEASE PRINT:

Name: _____________________________________________________________________
                 Last/Family                                       First                                            M.I.

Name on Badge ______________________________________________________________

Affiliation: ___________________________________________________________________

Address/MailStop:_____________________________________________________________

City/State/Zip/Country: _________________________________________________________

Phone (day time):________________________ Fax:__________________________________

IEEE Membership Number:___________________E-Mail:_____________________________

Dietary needs   :________ Vegetarian
 
                          ________ Spicy

PLEASE CIRCLE APPROPRIATE FEES:

Conference Registration Fees:        IEEE-Member                    Non-Member                 Full-time Student
                                                              US$/Rs.                           US$/Rs.                              US$

Advance Registration                          300/10500                       350/12250                            250
(until November 15, 1997)

On-site Registration                            350/12250                       400/14000                            300

The registration fee includes a copy of the proceedings, lunches, and refreshments on December 18, 19, and 20 and conference Banquet and Reception. Conference registration fee does not include participation in the tutorials. Tutorials are open to conference registrants only.

Tutorial Registration Fees:                IEEE-Member                   Non-Member                  Full-time Student
 (Per tutorial)                                        US$/Rs.                             US$/Rs.                                US$

Advance Registration                           75/2625                            100/3500                                75
(until November 15, 1997)

On-site Registration                            100/3500                            125/4375                              100

The tutorial registration fee includes participation in the tutorial, a copy of the tutorial notes and refreshments.

Tutorial 1 ___
Tutorial 2 ___
Tutorial 3 ___
Tutorial 4 ___
Tutorial 5 ___
Tutorial 6 ___
Tutorial 7 ___

Conference Registration Fee: __________________

Tutorial Registration Fee:        __________________

Total Amount Enclosed:          __________________

Bank/Institute issuing cheque: __________________

Cheque/Draft Number:           __________________

Payment must be enclosed. Please make cheques payable to International Conference on High Performance Computing. All cheques MUST be either in U.S. Dollars drawn on a U.S. Bank or in  Indian Rs. drawn on an Indian bank.

Participants currently residing in India may pay in Indian Rs., all others (including NRIs) must pay in U.S. Dollars. Written requests for refunds must be received (by the appropriate Finance Co-Chair) no later than Nov. 25, 1997. Refunds are subject to a US $50 (Rs. 1750) processing fee. All no-show registrants will be charged in full. Registration after November 15, 1997 will be accepted on-site only. Please do not send this registration form to the General Co-Chairs or to the Program Chair.

Please mail to:

HiPC '97
c/o Ajay Gupta
Computer Science Department
Western Michigan University
Kalamazoo, MI 49008, USA.
Email: hipc97@cs.wmich.edu
Fax: +1(616)387-3999

or

HiPC '97
c/o A. K. P. Nambiar
Software Technology Parks of India
Block III , KSSIDC Complex
KEONICS Electronics city
Hosur Road Bangalore 561229, INDIA
Email:nambiar@stpb.soft.net

Participants currently residing in India are requested to send their completed registration form to Mr. Nambiar, all others are requested to send it to Professor Ajay Gupta. Scholarships to a) full time students and b) faculty at Indian academic institutions and to researchers at Indian government establishments are available from agencies within India. For details contact Mr. C. P. Ravikumar (email: rkumar@ee.iitd.ernet.in). These scholarships are not available to participants from non-Indian institutions.
 

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Last Modified: October 31, 1997.