Student Research Symposium (SRS) @ HiPC 2025

HiPC 2025 will feature the 17^th Student Research Symposium (SRS) on High-Performance Computing, Data, and Analytics (HPC), aimed at stimulating and fostering student research and providing an international forum to highlight student research accomplishments. The symposium will be an integrated part of the main HiPC conference aiming to expose students to the best practices in HPC in academia and industry.

The symposium will feature student posters and provide students with other enriching experiences, such as workshops, industry exhibits, and demos. SRS 2025 will comprise mentoring sessions, a special keynote speech, an expert panel discussion, and lightning talks. The Conference Reception and multiple Student Symposium Poster Exhibit sessions will allow students to interact with HPC researchers and practitioners (and recruiters) from academia and industry. HiPC will provide limited travel support to one author of selected posters. Awards for Best Poster will be presented at the symposium.

SRS Schedule

Keynote Speaker

Rama K. Govindaraju, Nvidia – Senior Engineering Director, DGX Cloud Performance and Architecture

Title: Ethical Research in an AI Era

Abstract: AI is emerging as a powerful tool that can solve many challenging problems and substantially increase the engineering and research productivity. But how do we ensure we are using it ethically? Rama will discuss some of the experiences, some pitfalls to be aware of and steps that can be taken to leverage AI ethically to drive the next generation breakthroughs.

Bio: Rama is currently the Senior Engineering Director at Nvidia, California where he leads the DGX Cloud Performance and Architecture team. Earlier Rama built and led the team defining the methodology to inform the architecture and design of ~10 generations of servers, 5 generations of TPUs (Tensor Processing Unit for AI/ML workloads), Video transcoding accelerators, storage systems, all deployed at scale in Google data centers. Responsible for the efficient operation of the fleet from an end to end perspective enabling the virtuous cycle of HW-SW co-design. Defined the strategic vision for many critical aspects adopted at Google. Prior to that at IBM, Rama was a Distinguished Engineer and HPC Software Architect and led software architecture for 5 generations of Supercomputers at IBM.

Rama has a MS and PhD in Computer Science from Rensselaer Polytechnic Institute in New York and a BS in Computer Science from BIT Mesra, Ranchi, India.

List of Accepted Papers

1.  A Distributed Framework for Online Log Parsing with Large Language Model, Shruthi Kandukuri (National Institute of Technology Warangal (NITW)), Prince Kumar (National Institute of Technology Warangal (NITW)), Shubham Pahilwani (National Institute of Technology Warangal (NITW)), Umang Chourey (National Institute of Technology Warangal (NITW)), Sriram Kailasam (National Institute of Technology Warangal (NITW)) 
2. A GPU is All You Need: Rethinking Distributed and Out-of-Core GNN Training, Pranjal Naman (Indian Institute of Science), Yogesh Simmhan (Indian Institute of Science) 
3. Accelerating Chemical Kinetics Simulations via Dynamic Jacobians on CPUs and GPUs, Kunal Bahuguna (Siemens Technology and Services Pvt. Ltd.), Ved Vartak (Siemens Technology and Services Pvt. Ltd.), Subhajit Sanfui (Siemens Technology and Services Pvt. Ltd.), Ramsatish Kaluri (Siemens Technology and Services Pvt. Ltd.) 
4. Analysis of Streaming Inference Pipeline for Edge Accelerators, Mayank Arya (Indian Institute of Science), Priyanshu Pansari (Indian Institute of Science), Yogesh Simmhan (Indian Institute of Science) 
5. CentGNN: A Centrality-Driven Scheme for High-Performance Graph Neural Networks, Surendra Kumar Raut (IIT Bhilai), Kishan Tamboli (IIT Bhilai), Vishwesh Jatala (IIT Bhilai) 
6. Cryptographic Collapse Forecasting: A Strategic Shift to Quantum Security, Majid k (Indian Institute of Technology Dharwad), Sreejita Chatterjee (Indian Institute of Technology Dharwad), Aayush Kumar Jha (Indian Institute of Technology Dharwad), Koteshwararao Kondepu (Indian Institute of Technology Dharwad) 
7. FERN: Fast and Energy-Efficient Ring–Star Network Design Problem using MMACO, SUDHAKAR CHITTIMADHA (IIITDM, KANCHEEPURAM, CHENNAI), VENKATESH PANDIRI (IIITDM, KANCHEEPURAM, CHENNAI) 
8. FLandroid: Towards Federated Learning for Android Edge Devices, Amit Sharma (IIT Ropar), Chinmay Mahtre (IISc), Punit Rathore (IISc), Nitin Auluck (IIT Ropar), Yogesh Simmhan (IISc) 
9. Graph Coarsening for High-Performance GNN, Niharika Nayak (IIT Bhilai), Kishan Tamboli (IIT Bhilai), Vishwesh Jatala (IIT Bhilai) 
10. Mobility and Deadline-Aware RL-based Task Offloading Scheme in FC-IoT Networks, RAJASEKHAR DASARI (IIITDM Kancheepuram), Sanjeet Kumar Nayak (IIITDM Kancheepuram) 
11. Not All Clouds Are Transparent: Handling Unavailable Attributes in CSP Selection, Navya P (NIT Warangal), Sanjaya Kumar Panda (NIT Warangal), Rashmi Ranjan Rout (NIT Warangal) 
12. Pedagogy Meets AI & Systems: Towards Orchestrating Tutor Agents in Moodle using FaaS, Varad Kulkarni (Indian Institute of Science, Bangalore), Nikhil Reddy (Indian Institute of Science, Bangalore), Yogesh Simmhan (Indian Institute of Science, Bangalore) 
13. Securing Approximate Communication in NoC-based Systems, Tarun Sharma (IIITD), Deepank Grover (IIITD), Sujay Deb (IIITD)
14. Solving the Number Partitioning Problem with Hardware-Accelerated Probabilistic Computing, Kiran Magar (Indian Institute of Science), Utsav Banerjee (Indian Institute of Science) 
15. Success-Driven Bias-Aware Routing for Atomic Payments in Payment Channel Networks, Satyajit Mohapatra (IIITDM Kancheepuram), Sanjeet Kumar Nayak (IIITDM Kancheepuram) 
16. Towards building Trustworthy Data Provenance for Agentic Workflows, Aishwarya R Parab (BITS Pilani KK Birla Goa Campus), Prakhar Pradhan (BITS Pilani KK Birla Goa Campus), Manit Tanwar (BITS Pilani KK Birla Goa Campus), Yogesh Simmhan (Indian Institute of Science (IISc), Bangalore), Arnab K. Paul (BITS Pilani KK Birla Goa Campus) 
17. A one-stop DSL for all your GNN workloads, Anubhab . (Indian Institute of Technology Madras), Rupesh Nasre (Indian Institute of Technology Madras) 18. Density-Hierarchical Clustering with PRI Transform for Robust Radar Signal Deinterleaving, Isha Rajwar (IIT Hyderabad), Sathya Peri (IIT Hyderabad) 19. Distant History Branch Prediction Using Advanced Machine Learning Techniques, Bonthu Purna nand (IIT Tirupati), Jaynarayan T. Tudu (IIT Tirupati) 
18. Edge Pruning Methods for Distributed GNN, Shrashank Maravi (IIT Bhilai), Surendra Kumar Raut (IIT Bhilai), Kishan Tamboli (IIT Bhilai), Vishwesh Jatala (IIT Bhilai)
19. Energy-Aware Predictive Offloading in UAV for Containerized Smart Irrigation in IoT Agriculture, Abhishek Pandey (National Institute of Technology Karnataka), Sourav Kanti Addya (National Institute of Technology Karnataka) 
20. Frequency Throttling on GPUs, Sahil Kokare (Indian Institute of Technology Madras), Ricky Dev (KLA Corporation), Pradeep Ramachandran (KLA Corporation), Rupesh Nasre (Indian Institute of Technology Madras) 
21. Towards an Agentic AI Design across Edge and Cloud, Shiva Sai Krishna Anand Tokal (Indian Institute of Science), Vaibhav Jha (Indian Institute of Science), Anand Eswaran (IBM India Research Lab), Praveen Jayachandran (IBM India Research Lab), Yogesh Simmhan (Indian Institute of Science) 
22. Accelerating Parallel Particle-in-Cell Code using DPC++ SYCL on Heterogeneous Architectures, Abhimanyu Karia (Dhirubhai Ambani University), Libin Varghese (Dhirubhai Ambani University), Bhaskar Chaudhury (Dhirubhai Ambani University) 
23. Accelerating Robust Graph Representation Learning: A High-Performance Dual-Stream Contrastive Framework, Panchadip Bhattacharjee (Manipal Institute of Technology Bengaluru), Somyajeet Arukh (Manipal Institute of Technology Bengaluru), Sai Vishal Vishal Setti (Manipal Institute of Technology Bengaluru), Nishanth Shet (Manipal Institute of Technology Bengaluru), Gururaj H L (Manipal Institute of Technology Bengaluru) 
24. Accelerating Triton convolutions by exposing Shared Memory to the Programmer, Shourya Goel (Indian Institute of Technology, Roorkee), Ricky Dev (KLA), Pradeep Ramchandran (KLA) 
25. Architectural Design and Performance Analysis of a CUDA-Accelerated Framework for Collective Flocking Simulation, Pujita Satish Kumar (Thapar Institute of Engineering & Technology), Sumedha Khosla (Thapar Institute of Engineering & Technology), Saif Nalband (Thapar Institute of Engineering & Technology) 
26. AutoTuneGPU: An Energy-Aware Autotuning Framework for Machine Learning Workloads on GPUs, Ananya Krishna Srivastava (BITS GOA), Kumari Soumya (BITS Pilani)
27. Benchmarking WebAssembly on Edge Devices, Yash Kamble (Indian institute of Science, Bangalore), Sankalp Gawali (Indian institute of Science, Bangalore), Yogesh Simmhan (Indian institute of Science, Bangalore) 
28. Clustered Diagonal Segment Format (CDSF): A Practical and Memory-Efficient Storage for Sparse Diagonal and Banded Matrices, Omm Hari Shankar Sahoo (XIM University), Shreya Mathur (XIM University), Saloni Tripathy (XIM University), Chandan Misra (XIM University) 
29. Efficient On-Device Flicker Removal in High FPS Videos with Synthetic Data Generation, Hrishikesh Haritas (Ramaiah Institute of Technology), Jasmita T (Ramaiah Institute of Technology), Meeradevi K (Ramaiah Institute of Technology), Darshan Bankapure (Ramaiah Institute of Technology), Rahul K Vishal (Ramaiah Institute of Technology) 
30. Estimating Optimal GPU Occupancy Levels for Performant Matrix Multiplication Codes, Parikshit Gehlaut (Indian Institute of Technology Dharwad), Nikhil Hegde (Indian Institute of Technology Dharwad) 
31. Fast and Accurate MIS on Dynamic Graphs, Agam Harpreet Singh (Indian Institute of Technology Jodhpur), Neha Sharma (Indian Institute of Technology Jodhpur), Aditya Trivedi (Indian Institute of Technology Jodhpur), Dip Sankar Banerjee (Indian Institute of Technology Jodhpur) 
32. GPU Kernel-Level Characterization and Optimization of Transformer Models: From Baseline to LoRA Fine-Tuning, Sasi Snigdha Yadavalli (International Institute of Information Technology Bangalore), Badrinath Ramamurthy (International Institute of Information Technology Bangalore) 
33. GPU-Accelerated Neural ODEs for Stiff Dynamical Systems Using CVODES, Ved Vartak (Siemens Technology and Services Pvt. Ltd.), Subhajit Sanfui (Siemens Technology and Services Pvt. Ltd.), Ramsatish Kaluri (Siemens Technology and Services Pvt. Ltd.) 
34. HAMP-Net: GPU-Accelerated Hierarchical Adaptive Mixed-Precision Training with Gradient Compression for Image Classification., Somyajeet Arukh (Manipal Institute of Technology Bengaluru), Panchadip Bhattacharjee (Manipal Institute of Technology Bengaluru), Sai Vishal Setti (Manipal Institute of Technology Bengaluru), Nishanth Shet (Manipal Institute of Technology Bengaluru), Gururaj H L (Manipal Institute of Technology Bengaluru) 
35. Inductive Memory Networks for Dynamic PageRank, Sahil Narkhede (Indian Institute of Technology Jodhpur), Ankit Kumar (Indian Institute of Technology Jodhpur), Debmalya Bhattacharya (NIT Jamshedpur), Dip Sankar Banerjee (Indian Institute of Technology Jodhpur) 
36. Inference-aware Node Allocation to Reduce HPC Performance Variability, Arshit Narang (IIT Kanpur), Ruthvik Tunuguntla (IIT Kanpur), Pratham Sahu (IIT Kanpur), Preeti Malakar (IIT Kanpur) 
37. Neural Differential Equations with Integrated Control for Chemical Process Modeling, Sumeet Rodiya (Siemens Technology and Services Pvt. Ltd.), Ved Vartak (Siemens Technology and Services Pvt. Ltd.), Kunal Bahuguna (Siemens Technology and Services Pvt. Ltd.), Subhajit Sanfui (Siemens Technology and Services Pvt. Ltd.), Ramsatish Kaluri (Siemens Technology and Services Pvt. Ltd.) 
38. Towards Mitigation of Latency and Forgetting in Vehicular Federated Continual Learning, Harsh D. Chothani (BITS Pilani, KK Birla Goa Campus), Vimarsh Shah (BITS Pilani, KK Birla Goa Campus), Marichamy Kasi (BITS Pilani, KK Birla Goa Campus), Arnab K. Paul (BITS Pilani, KK Birla Goa Campus)
39. Towards Scalable Mining of Temporal Graph Motifs over Large-Scale Transaction Networks, Hrishikesh Haritas (Indian Institute of Science), Abhinav Rawat (Indian Institute of Science), Pranjal Naman (Indian Institute of Science), Ganesh Jambhrunkar (National Payments Corporation of India), Amit Khandelwal (National Payments Corporation of India), Saurav Singla (National Payments Corporation of India), Yogesh Simmhan (Indian Institute of Science)

Call for Papers

Papers are solicited in all areas of high-performance computing, data, and analytics, including but not limited to the topics mentioned in the HiPC Call for Papers.

IMPORTANT DATES:

Submissions open: September 1, 2025, AOE

Submission Deadline: September 30, 2025, AOE AOE October 10, 2025 (Friday) [Firm]

Accept/Reject Decision Notification: Nov 8, 2025, AOE

Camera-ready Deadline for the Abstract of Accepted Posters: Nov 21, 2025, AOE [Firm]

Symposium: Dec 17-20, 2025

ELIGIBILITY:

Submissions should have at least one student author during any part of the calendar year 2025. Submissions may have multiple student or non-student co-authors. Submissions must mark student authors with an asterisk (*). Student authors should also specify the degree they are pursuing.

SUBMISSION INSTRUCTIONS:

In order to be considered for a poster at the Student Research Symposium, authors must submit papers not exceeding two (2) single-spaced double-column pages (including references) using 10-point size font on 8.5×11-inch pages, with 1” margins on all sides (IEEE conference style). The IEEE conference style templates for MS Word and LaTeX provided by IEEE eXpress Conference Publishing are available for download. See the latest versions here.

Papers are to be submitted online in PDF format through https://ssl.linklings.net/conferences/HiPC/.

The submissions in SRS must not be under consideration for any track in any other conference including HiPC or journal. Any such submission will be desk rejected.  During submission, it needs to be marked whether the lead author is an undergraduate (B.E./B.Tech.), a postgraduate (M.E./M.Tech.) or a Ph.D. student.

A signed letter from the academic advisor needs to be submitted, which states that “the submitted work is original and the work is done by the student.”

The poster authors are encouraged to follow the following format for the two-page submission.

(1) Introduction (0.5 page): Answer the following in separate paragraphs.

• Clearly state the objective of the paper and motivate the specific problem your work is solving.
• Limitation of the state-of-art approaches. Briefly review the most relevant and most recent prior works. Clearly articulate the limitations of prior works and how your approach breaks away from those limitations.
• Key insights and contributions. Briefly articulate the major insights that enable your approach. Clearly specify the novelty of these insights and how they advance state-of-the-art.
• Limitations of the proposed approach. Clearly articulate the limitations of the proposed approach and identify avenues of future work.

(2) Design (0.5 page): Explain the overall design of your work with a brief explanation of the major components. It is better to include a small figure.

(3) Evaluation (0.5 page): Explain the testbed and include the major experimental results with graphs (if applicable).

(4) Conclusion and Future Work (0.3 page): Derive major conclusions of your work and specify future directions of the research.

(5) References (0.2 page): 4-5 major references for the work cited in the paper.

HiPC 2024 Student Research Symposium proceedings can be found here.

Disclaimer: For people without IEEE access, some sample 2-page posters are provided here which were accepted in HiPC 2024.

A two-page abstract of the selected posters will be published in the HiPC Workshop proceedings in IEEE Xplore. This will provide students with the flexibility to publish an extended version of their paper at other venues after benefiting from reviewer feedback. The papers will be reviewed by the reviewers and will be judged on technical merit, quality, relevance to the symposium, and related parameters. Plagiarism is prohibited in any form, especially verbatim reproduction from other published works. Plagiarized papers will be rejected, and the corresponding department and institution will be notified.

As per IEEE guidelines, the use of artificial intelligence (AI)–generated text in an article needs to be disclosed in the acknowledgements section of any submitted paper. The sections of the paper that use AI-generated text should have a citation to the AI system used to generate the text. For more information, please click here.

Facilities for displaying posters will be made available, and the exact specifications of the poster size will be provided later. At least one student author of each accepted paper must register and attend the conference to present their work. In addition, authors of a few selected posters will get a chance to present their work in the form of lightning talks. Papers with no-shows will be retroactively rejected.

TRAVEL SUPPORT:

HiPC will provide a limited travel scholarship to one student author of each accepted submission from an Indian university. There may be a small number of travel scholarships for international student authors. This scholarship will cover partial expenses for attending the conference. To get reimbursement of travel support, SRS organizers expect the selected students to attend the entire conference along with the SRS-specific activities. Further details on this scholarship and the application process will be provided later.

MENTORING SESSION:

Mentoring will be organized for the students selected for SRS, where the students will get an opportunity to meet senior researchers attending the HiPC conference. These mentoring sessions include a panel of experts providing their experiences in research and a lunch where a mentor will be matched with students. More mentoring opportunities are being planned for SRS students to get guidance in the world of R&D in high-performance computing.

SYMPOSIUM CO-CHAIRS:

Vishwesh Jatala, Indian Institute of Technology Bhilai, India

Sourav Kanti Addya, National Institute of Technology Karnataka, Surathkal, India

SYMPOSIUM PROGRAM COMMITTEE MEMBERS:

1. Khanh Nguyen, Texas A&M University, USA
2. Mehmet Belviranli, Colorado School of Mines, USA
3. Helen Xu, Georgia Tech, USA
4. TV Kalyan, IIT Ropar, India
5. Udit Agarwal, Siemens EDA, USA
6. Dip Sankar Banerjee, IIT Jodhpur, India
7. Nikhil Hegde, IIT Dharwad, India
8. Nitin Auluck, IIT Ropar, India
9. Vivek Kumar, IIIT Delhi, India
10. Sanket Tavarageri, Google, India
11. Awanish Pandey, IIT Roorkee, India
12. Anurag Satpathy, MUST, USA
13. Jayvant Anantpur, NVIDIA, India
14. Manu Awasthi, Ashoka University, India
15. Madhura Purnaprajna, AMD, India
16. Shirshendu Das, IIT Hyderabad, India
17. Sathya Peri, IIT Hyderabad, India
18. Alok Ranjan, Bosch, India
19. Debasree Das, University of Bamberg, Germany
20. Komal Kumari, Dassault Systemes Simulia Corp
21. Sai Charan Koduru, Google
22. Kishore Pusukari, Apple

Contact: <student_symposium at hipc dot org> for more details.